Designer productivity improves from designing an integrated circuit at a high level of abstraction and translating the abstract design into a layout of the integrated circuit. The abstract design is translated into a layout using synthesis, placement, and routing. However, synthesis, placement, and routing are iterative processes, because the first layout generally does not meet the performance requirements for the integrated circuit. Synthesis, placement, and routing are also time consuming and difficult. The tools for synthesis, placement, and routing require extensive designer expertise, and even expert designers cannot reliably predict the effects of a change made to meet performance requirements. Thus, synthesis, placement, and routing are time consuming processes of trial and error. The improved designer productivity from abstract design is lost when synthesis, placement, and routing require too many iterations.
The present invention may address one or more of the above issues.